The present disclosure generally relates to semiconductor structures, and particularly to a semiconductor structure including a carbon-doped cap on a raised active semiconductor region of a transistor, and methods of manufacturing the same.
Complementary metal oxide semiconductor (CMOS) circuits employ field effect transistors having various channel lengths. Field effect transistors including channels that display short channel effects are referred to as short channel devices, which typically have a channel length that is on the same order of magnitude as a minimum lithographic length (that can be printed by a single lithographic deep ultraviolet exposure). Field effect transistors including channels that do not display short channel effects are referred to as long channel devices, which typically have a channel length that is at least one order of magnitude longer than the minimum lithographic length.
In replacement gate field effect transistors, the height of the top surface of a planarization dielectric layer is affected by the local spacing between dummy gate structures. The variation in the height of the top surface of the planarization dielectric layer affects the depth of a contact via hole that is formed into a raised source region or into a raised drain region. Further, reactive ion etch (RIE) lag that depends on the pattern factor of contact via holes affects the depth of an overetch into the raised source region or the raised drain region. Specifically, a contact via hole formed for a long channel device tends to be deeper than a contact via hole formed for a short channel device because the density of the contact via holes is higher in a region for short channel devices.
Such variations in the depth of the contact via holes result in variations in the location of metal semiconductor alloy regions that are subsequently formed on source regions, drain regions, raised source regions, and/or raised drain regions. Such variations in the locations of metal semiconductor alloy regions result in leakage currents in source regions and drain regions, and especially in devices in which a metal semiconductor alloy region extends further into a semiconductor substrate and/or toward a p-n junction between a body region and a source region or between a body region and a drain region. Thus, a systematic method for reducing the variations in the height of metal semiconductor alloy regions is desired.